1. Field of the Invention
The present invention relates to a clock signal generating circuit for a dynamic type semiconductor memory device having an improved means for preventing failures caused by noises transmitted through an address strobe signal.
2. Description of the Related Art
Recently, in the field of the semiconductor memory device, the greater the miniaturization and integration, the narrower a space between wiring patterns. In this narrow space, the operation of the memory device is apt to be affected by noises caused by crosstalk between wiring patterns, or by differences in threshold voltage levels between external circuits. Particularly, in the dynamic type random access memory (below, DRAM), when these noises interfere with an address strobe signal which controls the read/write operations of the DRAM, a level of the address strobe signal is changed from a high level to a low level.
Selection of the word lines is based on the low level of the address strobe signal, and in the above case, a potential of a selected word line usually becomes an intermediate level even though a sense amplifier has not been activated. Consequently, information previously stored in a memory cell of the DRAM, which is connected to the selected word line, is destroyed by this intermediate level of the word line and thus failures in the read/write operations occur in the DRAM.
These problems are explained in detail hereinafter.